The present invention is directed, in general, to an integrated circuit and, more specifically, to a non-volatile semiconductor memory cell utilizing a trap charge layer and a channel-initiated secondary electron injection (CISEI) structure.
Erasable programmable read-only memory (EPROM) devices, including electrically erasable programmable read-only memory (EEPROM) devices, and flash EEPROM devices, are currently in extensive use today, being used in a multitude of telecommunications and computer applications. Because of small memory cell and array size, EEPROM memories have a significant cost advantage over conventional static random access memory (SRAM) devices. Furthermore, EPROM devices are more compatible with complimentary metal oxide semiconductor (CMOS) logic technologies than are dynamic random access memory (DRAM) devices, making them more suitable for system-on-a-chip embedded applications. However, there are problems to the widespread use of embedded EPROM devices that exist.
One such problem is the high row voltage required for programming. Programming flash EEPROM cells is done by raising cell voltage to above drain voltage (VDD), in order to impart enough energy for electrons in the channel of the transistor to become accelerated (i.e., xe2x80x9chotxe2x80x9d) and thereby be injected into the gate oxide. This is referred to as hot electron injection (CHEI). To accelerate the electrons to become hot, typical gate to source (Vgs) voltage is 7 to 12 volts, where typical VDD voltage may be 2.5 volts. Also, the drain to source voltage (Vds) needed is typically 6 to 10 volts. However, low voltage CMOS logic transistors are generally unable to generate and switch such voltages. Thus, in low voltage CMOS technologies, costly, additional processing is needed for fabrication of transistors able to withstand high voltage.
In addition to the requirements spelled out above, to generate high voltages at sufficient current, about 200 xcexcA/cell, complicated, large charge pumping circuits may be required to be manufactured within the CMOS device. These large charge pumping circuits are costly because of the relatively large amount of silicon area needed. The large charge pumping circuits also draw high operating power, which is in contrast to the need for the low power operation necessary for long battery life.
Another problem with the use of EPROM devices is the relatively long programming time, typically tens of microseconds. Programming times are lengthened by the reduction in channel current as the cell is programmed. As is known in the art, channel current is reduced as the device threshold is raised, which is done by the programming operation.
One attempt to overcome some of the limitations of previous EPROM devices has resulted in an EPROM device capable of programming with lower voltage and power. The industry developed a floating-gate flash EEPROM with channel-initiated secondary electron injection (CISEI). The CISEI device creates a programming environment in which the electrons injected into the floating-gate are secondary electrons heated by impact ionization feedback. The CISEI process is initiated by impact ionization in the channel of the device. Vertical electrical fields, perpendicular to the flow of electrons in the channel, impart energy to the secondary electrons, enabling their injection over a potential barrier and onto the floating-gate. Examples of these vertical fields include the field between the substrate and drain, and the field between the substrate and oxide interface near the drain edge. As a result, the CISEI device is capable of programming with lower drain to source voltage (xcx9c3.3 v), lower gate to source voltage (xcx9c5 v) and lower drain current (xcx9c20 xcexcA/cell). However, since channel conduction is necessary during programming, CISEI devices still require gate to source voltage higher than the desired programmed threshold voltage which is on the order of at least 1.5 volts above VDD. Even using CISEI programming, the required programming gate to source voltage is typically on the order of at least 2.5 volts above VDD, thus still requiring high voltage transistors and charge pumping circuits.
The CISEI device is also subject to undesirable xe2x80x9cover-erasurexe2x80x9d problems, which tends to age the EEPROM device prematurely as well as make the cells harder to program. Moreover, as described above, programming times are still lengthened by the reduction in channel current as the cell is programmed. A more detailed description of the CISEI process is set forth in U.S. Pat. No. 5,659,504, which is specifically incorporated herein by reference.
Accordingly, what is needed in the art is a semiconductor device that programs with gate to source and drain to source voltages of Vdd or less, does not have over-erasure problems and does not require the high programming power, voltages and long programming durations, as encountered in the prior art.
The present invention provides a semiconductor device that includes a tub region located in a semiconductor substrate, with the tub regions having a tub electrical contact connected thereto. The semiconductor device also includes a trap charge insulator layer located on the first insulator layer and a control gate located over the trap charge insulator layer. The control gate has a gate contact connected thereto for providing a second bias voltage to the semiconductor device that during programming is opposite in polarity to that of the first bias voltage.
The present invention also provides a method of manufacturing an integrated circuit. The method may include forming a tub region in a semiconductor substrate, with the tub region having a tub electrical contact connected thereto, forming a trap charge layer over the semiconductor substrate, and forming a control gate over the trap charge layer.